The present invention relates to a memory device having a plurality of storage elements and a plurality of replacement storage elements, each of which may be substituted for one of the storage elements.
In a memory circuit, e.g., a dynamic random access memory (DRAM) or a field programmable logic device, a plurality of memory cells are typically arranged in rows and columns for addressable access. For example, a DRAM chip may include 256 million cells (or more), which are arranged in an array of rows (activated by word lines) and columns (activated by bit lines).
In a conventional DRAM chip, one or more of the millions of cells of the memory array may be defective. In order to avoid the need to discard an entire DRAM chip, redundant cells are provided that may be substituted for the one or more defective cells. Usually, if a particular cell in the memory array is determined to be defective (e.g., during a manufacturing/test process), the entire row and/or column containing the defective cell is usually replaced by a redundant row and/or column. Herein, rows and/or columns of cells may be referred to as storage elements.
A conventional technique of substituting a defective storage element of the memory array with a replacement storage element involves using an enable fuse and address fuses associated with the replacement storage element. The address fuses contain the address of the defective storage element and the enable fuse indicates that the replacement of the defective storage element should be carried out. The enable fuse may take on an unfused state or may be permanently modified to take on a fused state. The enable fuse is modified (or set) to take on the fused state to indicate that the replacement storage element should replace the defective storage element of the memory array. The address of the defective storage element of the memory array is stored by setting certain of the address fuses associated with the replacement storage element. In use, when the defective storage element of the memory array is addressed, a comparison of the incoming address and the address stored in the address fuses will match. This indicates that the replacement storage element should be accessed instead of the defective storage element (so long as the enable fuse is set).
The conventional technique for replacing a defective storage element of the memory array with a replacement storage element does not permit the replacement to be reversed during the manufacture/testing process. This is so because once the enable fuse is set (fused) it cannot be unfused. Although the desirability of reversing the replacement process may appear counterintuitive, significant advantages in evaluating and performing manufacturing tests would be obtained if such reversal were possible.
In view of the foregoing, there is a need in the art for a new memory in which it is possible to replace certain storage elements of the memory array with other storage elements and, thereafter, to reverse such replacement and evaluate differences in the performance of the memory.
In accordance with at least one aspect of the present invention, a memory includes: a memory array having a plurality of storage elements; a plurality of replacement storage elements; a plurality of address storage units, each operable to store a replacement address associated with a respective one of the replacement storage elements; a plurality of enable storage units, each operable to store at least first and second enable bits associated with a respective one of the replacement storage elements; and a decode unit operable to (i) activate one of the replacement storage elements when the at least first and second enable bits associated therewith are in an enable state and an input address matches the replacement address associated with the replacement storage element, and (ii) deactivate the replacement storage element when the at least first and second enable bits associated therewith have changed to a disable state.
Preferably each of the plurality of enable storage units includes a first fusible link for storing the first enable bit and a second fusible link for storing the second enable bit. It is understood that each of the plurality of enable storage units may include one or more further fusible links for storing further enable bits. Each fusible link preferably has an unfused state that may be permanently modified to a fused state, and the first and second enable bits are in the enable state when either of the first and second fusible links is in the fused state. The first and second enable bits are preferably in the disable state when both the first and second fusible links are in the fused state. The decode unit preferably does not activate one of the replacement storage elements when the first and second fusible links associated therewith are both in the unfused state.
The plurality of storage elements of the memory array preferably includes row storage elements and column storage elements and the plurality of replacement storage elements includes row replacement storage elements and column replacement storage elements. The plurality of address storage units preferably includes (i) row address storage units, each operable to store a row replacement address associated with a respective one of the row replacement storage elements, and (ii) column address storage units, each operable to store a column replacement address associated with a respective one of the column replacement storage elements. The plurality of enable storage units preferably includes (i) row enable storage units, each operable to store at least first and second enable bits associated with a respective one of the row replacement storage elements, and (ii) column enable storage units, each operable to store at least first and second enable bits associated with a respective one of the column replacement storage elements.
In accordance with at least one further aspect of the present invention, a method of testing one or more memories is contemplated, where each memory includes a memory array having a plurality of storage elements and a plurality of replacement storage elements, each of which may be substituted for one of the storage elements of the given memory array when enabled. The method includes: conducting a first test on the plurality of storage elements of one or more memory arrays; enabling a first set of the replacement storage elements to replace a corresponding first set of the storage elements of the one or more memory arrays in response to results of the first test; conducting a second test on the plurality of storage elements of the one or more memory arrays as replaced by the first set of replacement storage elements; enabling a second set of the replacement storage elements to replace a corresponding second set of the storage elements of the one or more memory arrays in response to results of the second test; conducting a third test on the plurality of storage elements of the one or more memory arrays as replaced by the first and second sets of replacement storage elements and determining a first yield based thereon; disabling one of the first and second sets of replacement storage elements; conducting the third test on the plurality of storage elements of the one or more memory arrays as replaced by the remaining one of the first and second sets of replacement storage elements and determining a second yield based thereon; and comparing the first and second yields to determine the efficacy of the first or second test.
The one or more memories preferably further include a plurality of enable storage units, each operable to store at least first and second enable bits associated with a respective one of the replacement storage elements. The step of enabling the first set of the replacement storage elements preferably includes setting the respective at least first and second enable bits associated therewith to an enable state, and the step of enabling the second set of the replacement storage elements preferably includes setting the respective at least first and second enable bits associated therewith to an enable state. The step of disabling one of the first and second sets of replacement storage elements preferably includes setting the respective at least first and second enable bits associated therewith from the enable state to a disable state.
Other aspects, features, advantages, etc. will be apparent to one skilled in the art when the disclosure herein is taken in conjunction with the accompanying drawings.